FinFET devices have become a mainstream in semiconductor fabrication to achieve ever smaller device features and increased circuit performance. There are many challenges in fabricating these small FinFET devices in an integrated circuit (IC). For example, when forming contact features in FinFET devices, potential contact bottom voids have become a problem due to the topography on the wafer. Particularly, contact features situated between fins are relatively deeper and have higher aspect ratios than those situated on fins. Therefore, one issue associated with contact formation is that some contact holes are deep and narrow and it may be difficult for the contact features to completely fill these contact holes, thereby leaving voids under the contact features. These voids may be difficult to detect during the manufacturing stage, but they may cause problems such as circuit short or open over time. Accordingly, improvements in contact formation process are desired.